1. Field of the Invention
The invention relates to a method for fabricating semiconductor device, and more particularly, to a metal gate process.
2. Description of the Prior Art
In current semiconductor industry, polysilicon has been widely used as a gap-filling material for fabricating gate electrode of metal-oxide-semiconductor (MOS) transistors. However, the conventional polysilicon gate also faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of gate dielectric layer, reduces gate capacitance, and worsens driving force of the devices. In replacing polysilicon gates, work function metals have been developed to serve as a control electrode working in conjunction with high-K gate dielectric layers.
However, in current fabrication of high-k metal transistor, particularly during the stage for fabricating self-aligned contacts (SAC), part of the metal gates are typically removed and a protective mask layer is formed on the metal gates. The deposited protective mask layer is then planarized through chemical mechanical polishing (CMP) process so that the surface of the remaining mask layer is even with the surface of the interlayer dielectric (ILD) layer. This design however causes contact plugs formed thereafter to be too close to the metal gates thereby affecting performance of the device. Hence, how to improve the current process for fabricating metal gates for resolving this issue has become an important task in this field.